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#ifndef VM_C
#define VM_C
#include "badlib.h"
#include "compiler.c"
void
disassemble_instruction(Instruction instruction) {
switch (instruction.op) {
case OP_MOV8:
case OP_MOV16:
case OP_MOV32:
case OP_MOV64:
println("%s r%d, r%d", op_str[instruction.op], instruction.dst,
instruction.a, instruction.b);
break;
case OP_LD8K:
case OP_LD16K:
case OP_LD32K:
case OP_LD64K:
println("%s r%d, c%d", op_str[instruction.op], instruction.dst,
instruction.a, instruction.b);
break;
case OP_LD8I:
case OP_LD16I:
case OP_LD32I:
case OP_LD64I:
case OP_ST8I:
case OP_ST16I:
case OP_ST32I:
case OP_ST64I:
case OP_ADDI:
case OP_SUBI:
case OP_MULI:
case OP_DIVI:
case OP_MODI:
case OP_ADDFI:
case OP_SUBFI:
case OP_MULFI:
case OP_DIVFI:
case OP_MODFI:
case OP_EQI:
case OP_NEQI:
case OP_LTI:
case OP_GTI:
case OP_LEI:
case OP_GEI:
case OP_ANDI:
case OP_ORI:
println("%s r%d, r%d, c%d", op_str[instruction.op], instruction.dst,
instruction.a, instruction.b);
break;
case OP_LD8:
case OP_LD16:
case OP_LD32:
case OP_LD64:
case OP_ST8:
case OP_ST16:
case OP_ST32:
case OP_ST64:
case OP_ADD:
case OP_SUB:
case OP_MUL:
case OP_DIV:
case OP_MOD:
case OP_ADDF:
case OP_SUBF:
case OP_MULF:
case OP_DIVF:
case OP_MODF:
case OP_EQ:
case OP_NEQ:
case OP_LT:
case OP_GT:
case OP_LE:
case OP_GE:
case OP_AND:
case OP_OR:
println("%s r%d, r%d, r%d", op_str[instruction.op], instruction.dst,
instruction.a, instruction.b);
break;
case OP_HALT: println("%s", op_str[instruction.op]); break;
default: println("Unknown opcode %d", instruction.op); break;
}
}
void
disassemble_chunk(Chunk chunk) {
println("%s: =========== code ===========", chunk.file_name);
for (sz i = 0; i < array_size(chunk.code); i++) {
print("%s: %x{4}: ", chunk.file_name, i);
disassemble_instruction(chunk.code[i]);
}
if (array_size(chunk.constants) > 0) {
println("%s: ========= constants ========", chunk.file_name);
for (sz i = 0; i < array_size(chunk.constants); i++) {
println("%s: %x{2}: %x{8}", chunk.file_name, i,
chunk.constants[i]);
}
}
if (array_size(chunk.strings) > 0) {
println("%s: ========== strings =========", chunk.file_name);
for (sz i = 0; i < array_size(chunk.strings); i++) {
println("%s: %x{2}: %s", chunk.file_name, i, chunk.strings[i]);
}
}
}
#define N_CONST 256
typedef struct VM {
Chunk *chunk;
Constant regs[N_CONST];
Instruction *ip;
} VM;
void
vm_init(VM *vm, Chunk *chunk) {
assert(vm);
assert(chunk);
assert(chunk->code);
vm->chunk = chunk;
vm->ip = vm->chunk->code;
}
#define OP_BINARY(OP, TYPE) \
do { \
u8 dst = instruction.dst; \
u8 src_a = instruction.a; \
u8 src_b = instruction.b; \
vm->regs[dst].TYPE = vm->regs[src_a].TYPE OP vm->regs[src_b].TYPE; \
} while (0);
#define OP_BINARY_CONST(OP, TYPE) \
do { \
u8 dst = instruction.dst; \
u8 src_a = instruction.a; \
u8 src_b = instruction.b; \
vm->regs[dst].TYPE = \
vm->regs[src_a].TYPE OP vm->chunk->constants[src_b].TYPE; \
} while (0);
#include <math.h>
void
vm_run(VM *vm) {
assert(vm);
assert(vm->chunk);
assert(vm->ip);
println("VM running...");
while (true) {
Instruction instruction = *vm->ip++;
#if DEBUG == 1
print("IP: %d -> ", vm->ip - vm->chunk->code - 1);
disassemble_instruction(instruction);
#endif
switch (instruction.op) {
case OP_LD64K: {
u8 dst = instruction.dst;
u8 src_a = instruction.a;
vm->regs[dst].i = vm->chunk->constants[src_a].i;
} break;
case OP_EQ: OP_BINARY(==, i) break;
case OP_NEQ: OP_BINARY(!=, i) break;
case OP_LT: OP_BINARY(<, i) break;
case OP_GT: OP_BINARY(>, i) break;
case OP_LE: OP_BINARY(<=, i) break;
case OP_GE: OP_BINARY(>=, i) break;
case OP_AND: OP_BINARY(&&, i) break;
case OP_OR: OP_BINARY(||, i) break;
case OP_ADD: OP_BINARY(+, i) break;
case OP_SUB: OP_BINARY(-, i) break;
case OP_MUL: OP_BINARY(*, i) break;
case OP_DIV: OP_BINARY(/, i) break;
case OP_MOD: OP_BINARY(%, i) break;
case OP_ADDF: OP_BINARY(+, f) break;
case OP_SUBF: OP_BINARY(-, f) break;
case OP_MULF: OP_BINARY(*, f) break;
case OP_DIVF: OP_BINARY(/, f) break;
case OP_MODF: {
u8 dst = instruction.dst;
u8 src_a = instruction.a;
u8 src_b = instruction.b;
vm->regs[dst].f =
fmod(vm->regs[src_a].f, vm->chunk->constants[src_b].f);
} break;
case OP_HALT: {
println("VM HALT (int) -> %d", vm->regs[instruction.dst]);
println("VM HALT (float) -> %f", vm->regs[instruction.dst]);
return;
}
default: {
eprintln("unimplemented OP code: %d", instruction.op);
return;
}
}
}
}
#endif // VM_C
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