diff options
Diffstat (limited to 'src/vm.c')
-rw-r--r-- | src/vm.c | 47 |
1 files changed, 35 insertions, 12 deletions
@@ -39,6 +39,14 @@ disassemble_instruction(Instruction instruction) { | |||
39 | case OP_MULFI: | 39 | case OP_MULFI: |
40 | case OP_DIVFI: | 40 | case OP_DIVFI: |
41 | case OP_MODFI: | 41 | case OP_MODFI: |
42 | case OP_EQI: | ||
43 | case OP_NEQI: | ||
44 | case OP_LTI: | ||
45 | case OP_GTI: | ||
46 | case OP_LEI: | ||
47 | case OP_GEI: | ||
48 | case OP_ANDI: | ||
49 | case OP_ORI: | ||
42 | println("%s r%d, r%d, c%d", op_str[instruction.op], instruction.dst, | 50 | println("%s r%d, r%d, c%d", op_str[instruction.op], instruction.dst, |
43 | instruction.a, instruction.b); | 51 | instruction.a, instruction.b); |
44 | break; | 52 | break; |
@@ -60,6 +68,14 @@ disassemble_instruction(Instruction instruction) { | |||
60 | case OP_MULF: | 68 | case OP_MULF: |
61 | case OP_DIVF: | 69 | case OP_DIVF: |
62 | case OP_MODF: | 70 | case OP_MODF: |
71 | case OP_EQ: | ||
72 | case OP_NEQ: | ||
73 | case OP_LT: | ||
74 | case OP_GT: | ||
75 | case OP_LE: | ||
76 | case OP_GE: | ||
77 | case OP_AND: | ||
78 | case OP_OR: | ||
63 | println("%s r%d, r%d, r%d", op_str[instruction.op], instruction.dst, | 79 | println("%s r%d, r%d, r%d", op_str[instruction.op], instruction.dst, |
64 | instruction.a, instruction.b); | 80 | instruction.a, instruction.b); |
65 | break; | 81 | break; |
@@ -106,7 +122,7 @@ vm_init(VM *vm, Chunk *chunk) { | |||
106 | vm->ip = vm->chunk->code; | 122 | vm->ip = vm->chunk->code; |
107 | } | 123 | } |
108 | 124 | ||
109 | #define OP_ARITHMETIC(OP, TYPE) \ | 125 | #define OP_BINARY(OP, TYPE) \ |
110 | do { \ | 126 | do { \ |
111 | u8 dst = instruction.dst; \ | 127 | u8 dst = instruction.dst; \ |
112 | u8 src_a = instruction.a; \ | 128 | u8 src_a = instruction.a; \ |
@@ -114,7 +130,7 @@ vm_init(VM *vm, Chunk *chunk) { | |||
114 | vm->regs[dst].TYPE = vm->regs[src_a].TYPE OP vm->regs[src_b].TYPE; \ | 130 | vm->regs[dst].TYPE = vm->regs[src_a].TYPE OP vm->regs[src_b].TYPE; \ |
115 | } while (0); | 131 | } while (0); |
116 | 132 | ||
117 | #define OP_ARITHMETIC_CONST(OP, TYPE) \ | 133 | #define OP_BINARY_CONST(OP, TYPE) \ |
118 | do { \ | 134 | do { \ |
119 | u8 dst = instruction.dst; \ | 135 | u8 dst = instruction.dst; \ |
120 | u8 src_a = instruction.a; \ | 136 | u8 src_a = instruction.a; \ |
@@ -144,15 +160,23 @@ vm_run(VM *vm) { | |||
144 | u8 src_a = instruction.a; | 160 | u8 src_a = instruction.a; |
145 | vm->regs[dst].i = vm->chunk->constants[src_a].i; | 161 | vm->regs[dst].i = vm->chunk->constants[src_a].i; |
146 | } break; | 162 | } break; |
147 | case OP_ADD: OP_ARITHMETIC(+, i) break; | 163 | case OP_EQ: OP_BINARY(==, i) break; |
148 | case OP_SUB: OP_ARITHMETIC(-, i) break; | 164 | case OP_NEQ: OP_BINARY(!=, i) break; |
149 | case OP_MUL: OP_ARITHMETIC(*, i) break; | 165 | case OP_LT: OP_BINARY(<, i) break; |
150 | case OP_DIV: OP_ARITHMETIC(/, i) break; | 166 | case OP_GT: OP_BINARY(>, i) break; |
151 | case OP_MOD: OP_ARITHMETIC(%, i) break; | 167 | case OP_LE: OP_BINARY(<=, i) break; |
152 | case OP_ADDF: OP_ARITHMETIC(+, f) break; | 168 | case OP_GE: OP_BINARY(>=, i) break; |
153 | case OP_SUBF: OP_ARITHMETIC(-, f) break; | 169 | case OP_AND: OP_BINARY(&&, i) break; |
154 | case OP_MULF: OP_ARITHMETIC(*, f) break; | 170 | case OP_OR: OP_BINARY(||, i) break; |
155 | case OP_DIVF: OP_ARITHMETIC(/, f) break; | 171 | case OP_ADD: OP_BINARY(+, i) break; |
172 | case OP_SUB: OP_BINARY(-, i) break; | ||
173 | case OP_MUL: OP_BINARY(*, i) break; | ||
174 | case OP_DIV: OP_BINARY(/, i) break; | ||
175 | case OP_MOD: OP_BINARY(%, i) break; | ||
176 | case OP_ADDF: OP_BINARY(+, f) break; | ||
177 | case OP_SUBF: OP_BINARY(-, f) break; | ||
178 | case OP_MULF: OP_BINARY(*, f) break; | ||
179 | case OP_DIVF: OP_BINARY(/, f) break; | ||
156 | case OP_MODF: { | 180 | case OP_MODF: { |
157 | u8 dst = instruction.dst; | 181 | u8 dst = instruction.dst; |
158 | u8 src_a = instruction.a; | 182 | u8 src_a = instruction.a; |
@@ -165,7 +189,6 @@ vm_run(VM *vm) { | |||
165 | println("VM HALT (float) -> %f", vm->regs[instruction.dst]); | 189 | println("VM HALT (float) -> %f", vm->regs[instruction.dst]); |
166 | return; | 190 | return; |
167 | } | 191 | } |
168 | |||
169 | default: { | 192 | default: { |
170 | eprintln("unimplemented OP code: %d", instruction.op); | 193 | eprintln("unimplemented OP code: %d", instruction.op); |
171 | return; | 194 | return; |