1 files changed, 102 insertions, 0 deletions

diff --git a/src/common.h b/src/common.h
new file mode 100644
index 0000000..c306c6c
--- /dev/null
+++ b/src/common.h
@@ -0,0 +1,102 @@
+// Header definitions for memory mapped IO and common utilities.
+
+#include "shorthand.h"
+
+#define MEM_BASE 0x3F000000
+
+// GPIO registers.
+#define GPIO_GPFSEL0   ((vu32*)(MEM_BASE + 0x00200000))
+#define GPIO_GPFSEL1   ((vu32*)(MEM_BASE + 0x00200004))
+#define GPIO_GPFSEL2   ((vu32*)(MEM_BASE + 0x00200008))
+#define GPIO_GPFSEL3   ((vu32*)(MEM_BASE + 0x0020000C))
+#define GPIO_GPFSEL4   ((vu32*)(MEM_BASE + 0x00200010))
+#define GPIO_GPFSEL5   ((vu32*)(MEM_BASE + 0x00200014))
+#define GPIO_GPSET0    ((vu32*)(MEM_BASE + 0x0020001C))
+#define GPIO_GPSET1    ((vu32*)(MEM_BASE + 0x00200020))
+#define GPIO_GPCLR0    ((vu32*)(MEM_BASE + 0x00200028))
+#define GPIO_GPLEV0    ((vu32*)(MEM_BASE + 0x00200034))
+#define GPIO_GPLEV1    ((vu32*)(MEM_BASE + 0x00200038))
+#define GPIO_GPEDS0    ((vu32*)(MEM_BASE + 0x00200040))
+#define GPIO_GPEDS1    ((vu32*)(MEM_BASE + 0x00200044))
+#define GPIO_GPHEN0    ((vu32*)(MEM_BASE + 0x00200064))
+#define GPIO_GPHEN1    ((vu32*)(MEM_BASE + 0x00200068))
+#define GPIO_GPPUD     ((vu32*)(MEM_BASE + 0x00200094))
+#define GPIO_GPPUDCLK0 ((vu32*)(MEM_BASE + 0x00200098))
+#define GPIO_GPPUDCLK1 ((vu32*)(MEM_BASE + 0x0020009C))
+
+// Auxiliary registers (Mini UART and SPI).
+#define AUX_ENABLE      ((vu8*) (MEM_BASE + 0x00215004))
+#define AUX_MU_IO       ((vu8*) (MEM_BASE + 0x00215040))
+#define AUX_MU_IER      ((vu8*) (MEM_BASE + 0x00215044))
+#define AUX_MU_IIR      ((vu8*) (MEM_BASE + 0x00215048))
+#define AUX_MU_LCR      ((vu8*) (MEM_BASE + 0x0021504C))
+#define AUX_MU_MCR      ((vu8*) (MEM_BASE + 0x00215050))
+#define AUX_MU_LSR      ((vu8*) (MEM_BASE + 0x00215054))
+#define AUX_MU_MSR      ((vu8*) (MEM_BASE + 0x00215058))
+#define AUX_MU_SCRATCH  ((vu8*) (MEM_BASE + 0x0021505C))
+#define AUX_MU_CNTL     ((vu8*) (MEM_BASE + 0x00215060))
+#define AUX_MU_STAT     ((vu32*)(MEM_BASE + 0x00215064))
+#define AUX_MU_BAUD     ((vu16*)(MEM_BASE + 0x00215068))
+
+/**
+ * Set baud rate and characteristics (115200 8N1) and map to GPIO
+ */
+void uart_init()
+{
+    register unsigned int r;
+
+    /* initialize UART */
+    *AUX_ENABLE |=1;       // enable UART1, AUX mini uart
+    *AUX_MU_CNTL = 0;
+    *AUX_MU_LCR = 3;       // 8 bits
+    *AUX_MU_MCR = 0;
+    *AUX_MU_IER = 0;
+    *AUX_MU_IIR = 0xc6;    // disable interrupts
+    *AUX_MU_BAUD = 270;    // 115200 baud
+    /* map UART1 to GPIO pins */
+    r=*GPIO_GPFSEL1;
+    r&=~((7<<12)|(7<<15)); // gpio14, gpio15
+    r|=(2<<12)|(2<<15);    // alt5
+    *GPIO_GPFSEL1 = r;
+    *GPIO_GPPUD = 0;            // enable pins 14 and 15
+    r=150; while(r--) { asm volatile("nop"); }
+    *GPIO_GPPUDCLK0 = (1<<14)|(1<<15);
+    r=150; while(r--) { asm volatile("nop"); }
+    *GPIO_GPPUDCLK0 = 0;        // flush GPIO setup
+    *AUX_MU_CNTL = 3;      // enable Tx, Rx
+}
+
+/**
+ * Send a character
+ */
+void uart_send(unsigned int c) {
+    /* wait until we can send */
+    do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x20));
+    /* write the character to the buffer */
+    *AUX_MU_IO=c;
+}
+
+/**
+ * Receive a character
+ */
+char uart_getc() {
+    char r;
+    /* wait until something is in the buffer */
+    do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x01));
+    /* read it and return */
+    r=(char)(*AUX_MU_IO);
+    /* convert carrige return to newline */
+    return r=='\r'?'\n':r;
+}
+
+/**
+ * Display a string
+ */
+void uart_puts(char *s) {
+    while(*s) {
+        /* convert newline to carrige return + newline */
+        if(*s=='\n')
+            uart_send('\r');
+        uart_send(*s++);
+    }
+}