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authorBad Diode <bd@badd10de.dev>2023-08-31 09:24:29 +0200
committerBad Diode <bd@badd10de.dev>2023-08-31 09:24:29 +0200
commitea85184fdadf08760aa8f88871f96ddf8dde2914 (patch)
tree7cefaf976881d3d4a1035e2213689dfb982b8f88 /src/devices.c
parent7a02b549a38dadb48c43143ff94c9094abf25555 (diff)
downloaduxngba-ea85184fdadf08760aa8f88871f96ddf8dde2914.tar.gz
uxngba-ea85184fdadf08760aa8f88871f96ddf8dde2914.zip
Fix dup(2kr) and ovr(2kr) behaviour
Diffstat (limited to 'src/devices.c')
-rw-r--r--src/devices.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/src/devices.c b/src/devices.c
index c65d79b..2146bd3 100644
--- a/src/devices.c
+++ b/src/devices.c
@@ -109,16 +109,18 @@ void
109deo_system(u8 *dev, u8 port) { 109deo_system(u8 *dev, u8 port) {
110 switch(port) { 110 switch(port) {
111 case 0x3: { 111 case 0x3: {
112 // TODO: Rom bank switching (Needs testing). 112 // Rom bank switching (Needs testing).
113 u16 addr = PEEK2(dev + 0x2); 113 u16 addr = PEEK2(dev + 0x2);
114 if(uxn_ram[addr] == 0x01) { 114 if(uxn_ram[addr] == 0x01) {
115 u16 i, length = PEEK2(uxn_ram + addr + 1); 115 u16 length = PEEK2(uxn_ram + addr + 1);
116 u16 a_page = PEEK2(uxn_ram + addr + 1 + 2); 116 u16 a_page = PEEK2(uxn_ram + addr + 1 + 2);
117 u16 a_addr = PEEK2(uxn_ram + addr + 1 + 4); 117 u16 a_addr = PEEK2(uxn_ram + addr + 1 + 4);
118 u16 b_page = PEEK2(uxn_ram + addr + 1 + 6);
118 u16 b_addr = PEEK2(uxn_ram + addr + 1 + 8); 119 u16 b_addr = PEEK2(uxn_ram + addr + 1 + 8);
120 u8 *ram = uxn_ram;
119 u8 *rom = uxn_rom + (a_page % RAM_PAGES) * 0x10000; 121 u8 *rom = uxn_rom + (a_page % RAM_PAGES) * 0x10000;
120 for(i = 0; i < length; i++) { 122 for(size_t i = 0; i < length; i++) {
121 uxn_ram[(u16)(b_addr + i)] = rom[(u16)(a_addr + i)]; 123 ram[b_addr + i] = rom[a_addr + i];
122 } 124 }
123 } 125 }
124 } break; 126 } break;
@@ -177,8 +179,8 @@ dei_datetime(u8 *dev, u8 port) {
177 case 0x8: return t->tm_yday; 179 case 0x8: return t->tm_yday;
178 case 0x9: return t->tm_yday >> 8; 180 case 0x9: return t->tm_yday >> 8;
179 case 0xa: return t->tm_isdst; 181 case 0xa: return t->tm_isdst;
180 default: return dev[port];
181 } 182 }
183 return dev[port];
182} 184}
183 185
184u16 186u16