From 765dc3ab3d79bdca696a0d651385af3020c895c6 Mon Sep 17 00:00:00 2001
From: Bad Diode <bd@badd10de.dev>
Date: Sun, 28 May 2023 18:54:03 +0200
Subject: Add initial link cable clock sync

---
 src/sequencer.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'src/sequencer.c')

diff --git a/src/sequencer.c b/src/sequencer.c
index 867e686..7c989f2 100644
--- a/src/sequencer.c
+++ b/src/sequencer.c
@@ -19,6 +19,19 @@ bool redraw_bpm = true;
 bool redraw_piano_note = true;
 bool update_bpm = false;
 
+void
+gate_off(void) {
+    SIO_MODE = SIO_MODE_GP
+        | SIO_SC_OUT(1)
+        | SIO_SD_OUT(1)
+        | SIO_SI_OUT(0)
+        | SIO_SO_OUT(1)
+        | SIO_SC(0)
+        | SIO_SD(1)
+        | SIO_SO(0);
+    TIMER_CTRL_1 = 0;
+}
+
 void
 play_step(void) {
     Pattern *pat = &patterns[current_pattern];
@@ -135,6 +148,22 @@ play_step(void) {
         SOUND_NOISE_CTRL = 0;
         SOUND_NOISE_FREQ = 0;
     }
+    // TODO: This should be configurable e.g. po needs a 1 each 2 to sync
+    // exactly, but we can also just want a pseudo clock divider.
+    if (step_counter % 2 == 0) {
+        SIO_MODE = SIO_MODE_GP
+            | SIO_SC_OUT(1)
+            | SIO_SD_OUT(1)
+            | SIO_SI_OUT(0)
+            | SIO_SO_OUT(1)
+            | SIO_SC(1)
+            | SIO_SD(1)
+            | SIO_SO(0);
+        int n_ticks = -244181 / 600;
+        irs_set(IRQ_TIMER_1, gate_off);
+        TIMER_DATA_1 = n_ticks;
+        TIMER_CTRL_1 = TIMER_CTRL_IRQ | TIMER_CTRL_ENABLE | TIMER_CTRL_FREQ_3;
+    }
     step_counter = (step_counter + 1) % 16;
     redraw_piano_note = true;
 }
-- 
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